In designing an integrated circuit (IC) device, engineers or designers typically rely on computer design tools to help create an IC schematic or design, which can include a multitude of individual devices, such as transistors, coupled together to perform a certain function. To actually fabricate the IC device in or on a semiconductor substrate, the IC device schematic must be translated into a physical representation or layout, which itself can be transferred onto the surface of the semiconductor substrate. Computer-aided design (CAD) tools can be used to assist layout designers with translating the discrete circuit elements into shapes, which will embody the devices themselves in the completed IC device. These shapes make up the individual components of the circuit, such as gate electrodes, diffusion regions, metal interconnects and the like.
The software programs employed by the CAD systems to produce layout representations are typically structured to function under a set of predetermined design rules in order to produce a functional circuit. Often, the design rules are determined by certain processing and design limitations based roughly on the patternability of layout designs. For example, design rules may define the space tolerance between devices or interconnect lines.
Once the layout of the circuit has been created, the next step to manufacturing the IC device is to transfer the layout onto a semiconductor substrate. Optical lithography or photolithography is a well-known process for transferring geometric shapes onto the surface of a semiconductor wafer. The photolithography process generally begins with the formation of a photoresist layer on the top surface of a semiconductor substrate or wafer (or some intermediate layer). A reticle or mask having light non-transmissive opaque regions, which are often formed of chrome, and light transmissive clear regions, which are often formed of quartz, is then positioned over the photoresist-coated wafer.
The mask is placed between a radiation or light source, which produces light of a pre-selected wavelength (e.g., ultraviolet light) and geometry, and an optical lens system, which may form part of a stepper or scanner apparatus. When light from the light source is directed onto the mask, the light is focused to generate a reduced mask image on the wafer, typically using the optical lens system, which contains one or several lenses, filters and/or mirrors. The light passes through the clear regions of the mask to expose the underlying photoresist layer and is blocked by the opaque regions of the mask, leaving the underlying portion of the photoresist layer unexposed. The exposed photoresist layer can then be developed, typically through chemical removal of the exposed or unexposed regions of the photoresist layer. The end result is a semiconductor wafer coated with a photoresist layer exhibiting a desired pattern, which defines geometries, features, lines and shapes of that layer. This pattern can then be used for etching underlying regions of the wafer.
Once a wafer of IC devices is manufactured, experimental testing and/or inspection of the manufactured devices can be performed to verify that the manufactured devices are within specification limits set by the device design and/or layout. This testing, which is commonly referred to as metrology, can include obtaining critical dimension (CD) measurements of structures across the device, obtaining scanning electron microscopy (SEM) images of various regions across the device as well as other optical and electrical measurements.
Currently, there is no convenient way to assign errors detected during metrology (wafer metrology or reticle metrology) to a specific location within the layout. For example, a SEM image may show a defect within a structure on the patterned wafer. However, the corresponding location within the layout cannot be determined without considerable time and expense. Further, there is non-coordination of locations across the various spaces involved in IC device design, manufacture and testing (i.e., circuit design, circuit layout, reticle manufacture, and wafer patterning). Therefore, when an error is detected during metrology, there is no practical way to trace it across the different spaces involved in IC device design and manufacture.
Further, in an effort to continue device downscaling, and as IC device design and manufacture technology progresses and is further automated, the user can be presented with prodigious amounts of data, including parametric design rule variation test layouts, optical proximity correction (OPC) and optical rule checking (ORC) simulation results, and metrology test results. Currently, there is no way to efficiently process or otherwise link all of this data, which results in incomplete characterization of the manufacturability of a given process.
Accordingly, a need exists in the art for an improved method and system for metrology recipe generation and review and analysis of design, simulation and metrology results.